1. Field of the Invention
The present invention generally relates to output latch circuits and semiconductor devices, and particularly relates to an output latch circuit for outputting complementary data and a semiconductor memory device having such an output latch circuit therein.
2. Description of the Related Art
FIG. 1 shows an output latch circuit that outputs complementary data in a related-art semiconductor memory device. This output latch circuit includes clocked gate inverters 11 through 14 and inverters 15 through 19. Complementary signals SOX and SO that are output from a sense amplifier are input to the clocked gate inverters 11 and 12, respectively. (xe2x80x9cXxe2x80x9d at the end of a signal name indicates a negative logic signal that is an inverse of the signal without xe2x80x9cXxe2x80x9d at the end of the signal name thereof). The clocked gate inverter 13 and the inverter 15 together form a latch, and the clocked gate inverter 14 and the inverter 16 together form another latch.
Output enable signals OE and OEX are supplied to the clocked gate inverters 11 through 14 as gate signals. Each clocked gate inverter inverts an input signal, and supplies the inverted signal as an output signal when the output enable signal OE is HIGH.
FIG. 2 is a timing chart showing operation timings of the output latch circuit of FIG. 1. As shown in FIG. 2, the complementary signals SO and SOX that are output from an sense amplifier start appearing around timing T1, and are sensed by the sense amplifier to be locked to either a HIGH level or a LOW level. At timing T2, the output enable signal OE is supplied. At timing T4 that is two delays after the timing T2 where one delay corresponds to a delay by one gate, latch outputs OL and OLX appear. The reason why there are two gate delays is that the sense amplifier output SO, for example, appears as the latch output OLX after passing through two gates that are the clocked gate inverters 12 and 16. Output signals OUT and OUTX of the output latch circuit appear at timing T5 from the inverters 18 and 17, respectively.
As is understood from the above description, in the related-art output latch circuit of FIG. 1, data is output following a timing margin from timing T1 to timing T2 and three gate delays from timing T2 to timing T5 after the data of the sense amplifier is locked. In an attempt to reduce the delay of data output timing as described above, an output latch circuit has been provided that does not rely on output enable signals.
FIG. 3 shows an output latch circuit that does not rely on output enable signals in a related-art semiconductor memory device. The output latch circuit of FIG. 3 includes NAND circuits 21 and 22 and inverters 23 and 24. The NAND circuits 21 and 22 have outputs thereof that are input to each other, thereby together forming a latch. Complementary signals SOX and SO that are output from a sense amplifier are input to the remaining input nodes of the NAND circuits 21 and 22.
FIG. 4 is a timing chart showing operation timings of the output latch circuit of FIG. 3. As shown in FIG. 4, the complementary signals SO and SOX that are output from an sense amplifier start appearing around timing T1, and are sensed by the sense amplifier to be locked to either a HIGH level or a LOW level. At timing T2 that is one gate delay after the timing T1, one of the latch outputs OL and OLX appears. At timing T3 that is one gate delay after the timing T2, the other one of the latch outputs OL and OLX appears. The reason why the circuit operates in the way described above is that one of the NAND circuits 21 and 22 has an output thereof changed first, and, then, this output change propagates through the other NAND circuit to appear as an output change of this NAND circuit. Thereafter, output signals OUT and OUTX of the output latch circuit come out from the inverters 24 and 23, respectively. One of the output signals OUT and OUTX appear at timing T3, and the other appear at timing T4.
As is understood from the above description, in the related-art output latch circuit of FIG. 3, one of the output data is output following two gate delays from timing T1 to timing T3 after the data of the sense amplifier is locked, and the other one of the output data is output following three gate delays from timing T1 to timing T4.
In the related-art output latch circuit, a four gate delays are generated if the circuit configuration employs the output enable signals, and three gate delays are necessary before all the data is output in the circuit configuration that does not rely on the output enable signals.
Accordingly, there is a need for an output latch circuit that outputs complementary data at high speed, and, also, there is a need for a semiconductor device that is provided with such an output latch circuit.
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Accordingly, it is another and more specific object of the present invention to provide a semiconductor device provided with an output latch circuit that outputs complementary data at high speed.
In order to achieve the above objects according to the present invention, a semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.
In the semiconductor device as described above, the latch circuits are reset at the same timing as the activation of the amplifier circuit, and latch the outputs of the amplifier circuit by a latch including only one intervening gate from the input to the output thereof. Because of this configuration, a time period that passes before the completion of latching is one gate delay after the locking of outputs of the amplifier circuit. Even if the outputs of the latch circuits are output via output buffers having one gate delay, data is output two gate delays after the locking of output of the amplifier circuit.
In detail, each of the latch circuits includes a NAND circuit having two inputs, one of which receives the corresponding one of complementary data outputs supplied from the amplifier circuit, an inverter which receives an output of the NAND circuit as an input thereof, and supplies an output thereof to another one of the two inputs of the NAND circuit, and two transistors connected in series between the output of the NAND circuit and a ground, one of the two transistors receiving at a gate thereof the corresponding one of complementary data outputs supplied from the amplifier circuit, another one of the two transistors receiving the activation signal at a gate thereof, wherein the output of the NAND circuit serves as the output of each of the latch circuits.
Further, in order to eliminate a risk that the latch circuits latch erroneous data in response to the shift toward a LOW level of an amplifier circuit output that is supposed to be HIGH, the NAND circuit described above includes a PMOS transistor which receives the output of the inverter at a gate thereof, and has a source thereof connected to a power supply voltage and a drain thereof connected to the output of the NAND circuit, a first NMOS transistor which receives the output of the inverter at a gate thereof, and has a drain thereof connected to the drain of the PMOS transistor, a second NMOS transistor which receives at a gate thereof the corresponding one of complementary data outputs supplied from the amplifier circuit, and has a drain thereof connected to the source of the first NMOS transistor and a source thereof connected to the ground, and a PMOS transistor which receives at a gate thereof the corresponding one of complementary data outputs supplied from the amplifier circuit, and has a drain thereof connected to the output of the NAND circuit and a source thereof connected to another one of the complementary data outputs supplied from the amplifier circuit.
In the configuration described above, the latter PMOS transistor receives a sense amplifier output SO at the gate thereof, and receives a sense amplifier output SOX at the source thereof. When the sense amplifier output SO is pulled toward to the LOW level, the sense amplifier output SO and the sense amplifier output SOX maintain the same voltage level. There is thus no voltage difference between the gate and the source of this PMOS transistor, so that no threshold voltage is provided to make the transistor conductive. As a result, the output of the NAND circuit does not erroneously become HIGH to latch erroneous data.
Further, in order to eliminate a risk that the latch circuits latch erroneous data in response to the shift toward a LOW level of an amplifier circuit output that is supposed to be HIGH, each of the latch circuits includes a first NAND circuit having two inputs, one of which receives the corresponding one of complementary data outputs supplied from the amplifier circuit, a second NAND circuit which has an input thereof receiving an output of the first NAND circuit, and has another input thereof receiving a reset signal, an output of the second NAND circuit being supplied to another one of the two inputs of the first NAND circuit, and two transistors connected in series between the output of the first NAND circuit and a ground, one of the two transistors receiving at a gate thereof the corresponding one of complementary data outputs supplied from the amplifier circuit, and another one of the two transistors receiving the activation signal at a gate thereof, wherein the output of the first NAND circuit serves as the output of each of the latch circuits, and a latch function of each of the latch circuits is suspended during an activation period of the reset signal.
In the configuration described above, the data latch function of the latch circuits is temporarily suspended to eliminate a risk that the latch circuits latch erroneous data when the sense amplifier output that is supposed to be HIGH is pulled toward to the LOW level.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.